With non-volatile memory devices, stored data may be maintained even when an external power supply is interrupted. A nonvolatile flash memory device may have a floating gate, and a flash memory device may be capable of electrically writing and erasing data while providing non-volatile storage. In general, a flash memory device includes a floating gate capable of storing a charge, and a control gate electrode controlling the floating gate.
A coupling ratio of a flash memory cell may be enhanced to increase integration and to reduce power consumption. A coupling ratio can be defined as a ratio of a voltage induced at the floating gate with respect to an operating voltage applied to the control gate electrode. That is, as the coupling ratio increases, the voltage induced at the floating gate may increase. Accordingly, the operating voltage applied to the control gate electrode can be reduced by increasing the coupling ratio. By doing so, a level of integration of a flash memory device may be increased while power consumption may be reduced. The coupling ratio may be increased by increasing static capacitance between the control gate electrode and the floating gate. With highly integrated semiconductor devices, however, it may be difficult to increase static capacitance between a control gate electrode and a floating gate within a limited area. Moreover, high levels of integration may cause other problems.
At present, a stack type flash memory device may provide relatively high integration. More particularly, a stack type flash memory device has a structure such that a floating gate and a control gate electrode are sequentially stacked.
FIG. 1A is a cross sectional view of a flash memory device having a stack structure, and FIG. 1B is a sectional view taken along line I-I' of FIG. 1A.
Referring to FIGS. 1A and 1B, a device isolation layer 2 on a semiconductor substrate 1 defines an active region. Floating gates 4 are spaced apart from each other on the active region. Control gate electrodes 6 are on respective floating gates 4. The control gate electrodes 6 cross an upper surface of the active region, and the control gate electrodes 6 are arranged in parallel.
Tunnel oxide layers 3 are between the respective floating gates 4 and the active region, and ONO (oxide-nitride-oxide) layers 5 are between the respective floating gates 4 and control gate electrodes 6. That is, the floating gates 4 are electrically isolated from the active region and the control gate electrodes 6 by the tunnel oxide layers 3 and the ONO layers 5 so that the floating gates 4 are electrically isolated. Source/drain regions are formed in the active region at both sides of the floating gates 4. Each floating gate 4 has a pair of first sidewalls adjacent to the device isolation layer 2, and a pair of second sidewalls adjacent to the source/drain regions 7.
The control gate electrodes 6 cover the first sidewalls of the respective floating gates 4, with the ONO layers 5 therebetween. As a result, a static capacitance between the control gate electrode 6 and the floating gate 4 may be increased to increase a coupling ratio of the flash memory cell.
A further increase of the coupling ratio in a limited area may be provided by increasing the thickness of the floating gate 4. In this case, the area of the sidewalls of the floating gate 4 may be increased, so that static capacitance between the control gate electrodes 6 and the floating gates 4 is increased.
As the thickness of the floating gates 4 increases, an area of the second sidewalls of the floating gate 4 may also increase. As the area of the second sidewalls of the floating gates 4 increases, an overlapping area between the adjacent floating gates 4 may increase, so that a parasitic capacitance between the adjacent floating gates 4 may increase. As the parasitic capacitances increase, a failure rate of the flash memory device may increase. For example, when a write or erase operation is performed for a selected floating gate 4, another floating gate 4 adjacent to the selected floating gate 4 may be soft-written or soft-erased. Also, the parasitic static capacitance may influence the coupling ratio. That is, as the parasitic static capacitance increases, the coupling ratio may decrease.